The present invention relates to a semiconductor device and a method for manufacturing the same, which form a recess gate region on a semiconductor substrate, form an isolation layer isolated from the recess gate region using a high-temperature thermal process, and guarantee a larger channel region by filling the isolation layer with a gate electrode material, so that a cell current is increased and on/off characteristics of a transistor are improved.
An important parameter among a plurality of parameter requisites for a process for manufacturing a transistor of a semiconductor device is a threshold voltage (Vt). The threshold voltage is a variable that depends on a thickness of a gate oxide layer, a channel doping density, an oxide charge, and a material used for a gate. The smaller the size of a device, the larger a difference between the threshold voltage and a theoretical threshold value. In more detail, there arises a variety of problems in which the threshold voltage is not identical to a theoretical threshold value as the size of a semiconductor device is gradually decreased. An example of such a problem is a short channel effect that is generated as a gate channel length is decreased.
As the semiconductor device becomes highly integrated, a nano (nm)-sized device requires not only an increase in speed but also a capability of operating at a low voltage of 1V˜2V, and thus requires a low threshold voltage. However, if the threshold value is further decreased, it is impossible to control the device due to the short channel effect. In addition, the short channel effect can cause a Drain Induced Built-in Leakage (DIBL) caused by a hot carrier.
Although a variety of research are being conducted to reduce the short channel effect, a solution capable of reducing the short channel effect remains unfinished as the semiconductor device continues to become highly integrated.
Although there is research aimed to find out the solution by adjusting the doping density, these methods do not completely solve the short channel effect. A variety of these research methods are well known to those skilled in the art. For example, a method for forming a Super Steep Retrograde Channel (SSR) through a Vertically Abrupt Channel Doping (VACD), a method for forming an ion implant channel, a Laterally Abrupt Channel Doping (LACD) method, a method for forming a channel including a halo structure through a Large Angle Tilt Implant (LATI), etc. may be used.
However, the reduction in thickness of a gate oxide layer and the reduction in short channel effect are basically limited. In recent times, in order to obviate the above-mentioned limitations, a channel length is guaranteed using a recess gate, and a degree of freedom of a cell junction is increased, and a channel width is increased using a fin-gate technology, such that a cell current is guaranteed and a leakage current is adjusted.
However, the above-mentioned technology that uses the recess gate and the fin gate technology may have a certain disadvantage for a device with a cell size of 30 nm or less.